By Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
This booklet constitutes the refereed lawsuits of the eleventh foreign Symposium on utilized Reconfigurable Computing, ARC 2015, held in Bochum, Germany, in April 2015.
The 23 complete papers and 20 brief papers offered during this quantity have been rigorously reviewed and chosen from eighty five submissions. they're prepared in topical headings named: structure and modeling; instruments and compilers; platforms and functions; network-on-a-chip; cryptography purposes; prolonged abstracts of posters. additionally, the ebook comprises invited papers on funded R&D - operating and accomplished initiatives and Horizon 2020 funded projects.
Read or Download Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings PDF
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Additional resources for Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
Speciﬁcally, we have proposed two methods to estimate required cache depth to avoid all capacity misses, and a way of enhancing the matrix representation to avoid all cold misses. Our experiments with a suite of large sparse matrices indicate that the scheme can service random accesses to the result vector with no or few stalls, while avoiding cold miss penalties that hamper traditional hardware caches. Future work will include evaluating the vector caching scheme in a complete FPGA SpMV accelerator context.
Changing the input vector 10K times reveals the variation as illustrated in the histograms of Fig. 8. The X-axis of each histogram represents the number of idle cycles in an idle period and the Y-axis is the number of input vectors that led to that number of idle cycles. The ﬁrst idle period does not show any variation, however, the second and third idle periods do show variation. In both cases, the periods were either 5 cycles long or 100 cycles long, depending on one of the input signals. For period 2, about 40% of input samples led to an idle period of 5 cycles.
However, the HSPICE simulated architecture parameter values, given in Table. 1, allows us to quantify the impact of hierarchical powergating. 2 Hierarchical Power-Gating Evaluation In order to quantify the impact of hierarchical power-gating, we apply the following power-gating policies to the parent and child accelerators in CHStone benchmarks suite  and compare their impact: Accelerator-Level Power-Gating; Policy-P1: In this policy, the entire accelerator, including all the sub-accelerators of this accelerator, is considered as one power-gating unit.