By Jesus Carretero, Javier Garcia-Blas, Ryan K.L. Ko, Peter Mueller, Koji Nakano
This booklet constitutes the refereed lawsuits of the sixteenth overseas convention on Algorithms and Architectures for Parallel Processing, ICA3PP 2016, held in Granada, Spain, in December 2016.
The 30 complete papers and 22 brief papers offered have been rigorously reviewed and chosen from 117 submissions. They hide many dimensions of parallel algorithms and architectures, encompassing primary theoretical ways, functional experimental tasks, and advertisement parts and structures attempting to push past the bounds of current applied sciences, together with experimental efforts, leading edge platforms, and investigations that establish weaknesses in present parallel processing technology.
Read Online or Download Algorithms and Architectures for Parallel Processing: 16th International Conference, ICA3PP 2016, Granada, Spain, December 14-16, 2016, Proceedings PDF
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Additional resources for Algorithms and Architectures for Parallel Processing: 16th International Conference, ICA3PP 2016, Granada, Spain, December 14-16, 2016, Proceedings
To check the constraints for a combination (Ss , Sls , Fs , Fl ), the program is run with a proﬁler using the same inputs as the original run. The proﬁler proﬁles Ss , Sls , Fs , and Fl instructions. It also proﬁles any other instruction that accesses the same locations as these instructions. For each of these instructions, it records the instruction and memory address and the id of the executing thread. The proﬁler captures the order of execution of diﬀerent memory access instructions from the same thread.
However, most commercial architectures sacriﬁce SC to improve performance. For example, x86 implements a memory model similar to TSO  which allows a later load operation to bypass an earlier store operation from the same processor. The overlapping and reordering of memory accesses can lead non SC behavior of a program, referred to as an SC Violation (SCV). Consider Dekker’s algorithm in Fig. 1(a). Processor P0 ﬁrst writes ﬂag1 (I1) and then reads ﬂag2 (I2) but P1 ﬁrst writes ﬂag2 (J1) and then reads ﬂag1 (J2).
Dissector, targets TSO memory model for its widespread availability. In addition, it is streamlined for detecting 2 processor SCVs because of their sweeping majority [14,22]. Dissector exploits the fact that TSO allows only one type of memory reordering a load bypassing an earlier store. Therefore, an SCV can occur when the earlier bypassed store communicates with some remote load or store. Whenever a write miss (due to a store, S1) invalidates (step 1 in Fig. 1(c)) a line accessed by a load L0, the processor P0 responds (step 2) with a count of stores.